Thermal control is a critical consideration in any microelectronics design process. Various packaging configurations require different thermal environments to prevent device failure and to ensure predictable operating parameters. Therefore, designers of microelectronics equipment must be equipped with a range of thermal control techniques.
A conventional electronic system includes four levels of packaging complexity, each requiring special thermal considerations. The first packaging level is the chip package. Level 1 thermal packaging is concerned with conducting heat from a device (e.g., an integrated circuit (IC) chip, die or other device) to the surrounding package. The second level of packaging involves the devices attached to the printed circuit board (PCB). Level 2 addresses spreading heat from a PCB by conduction in the PCB, convection to the ambient air, or transport to the edge of the PCB. The third level is the backplane or motherboard which connects multiple PCBs, and the fourth level defines the box, rack or cabinet which houses the entire system. Level 3 and 4 typically involves the use of active thermal control systems, such as, air handling systems, refrigeration systems, etc. The principles of the present invention have particular applicability to Levels 1 and 2.
The quantity of heat that must be removed from the device has increased over the past several decades, despite the drop in transistor switching energy. Transistor switching energy has dropped from more than 1 nanoJoule in 1960 to 10 picoJoules in the early 1990s. However, cooling requirements have not diminished because device densities and operating speeds have increased. Accordingly, chip heat removal has risen from on the order of 0.1-0.3 Watts (W) in the 1960s to 15-30 W for commercial equipment in early 1990s, and could be as much as 150 W or more by the year 2000.
One problem relating to thermal control is device failure. For example, each IC contains millions of individual elements (e.g., transistors, gates, etc.). While individually these solid state elements are typically highly reliable, each with a failure rate on the order of one in one trillion devices, the increase in the number of elements per chip and number of chips per system increases the likelihood of system failure. Studies have shown that element-related functional failures exhibit a strong relationship to operating temperature. For example, a 10-20 degree Celsius increase in chip temperature may double the element failure rate under some conditions. At the packaging level, increasing structural complexity of IC packages and PCBs has increased the risk of thermally-induced failures from thermal-stress fracture of leads, joints and seals, melting of solders, cracking, etc. Furthermore, stabilization of component temperature has long been known to reduce failure rates in electronic systems.
Another problem related to thermal control is the variability of the package temperature and corresponding variability in performance. Thermal design considerations must reduce the temperature variations within the package for consistent and reliable performance. For example, complementary metal-oxide-semiconductor (CMOS) circuit speed is dependent on temperature. Thus, an increase or decrease in temperature may affect cycle times or timing margins.
Several proposed solutions to the above thermal control design challenges are in common usage today. Among passive thermal control techniques, ambient air is the most common and preferred coolant. Heat sinks, which utilize finned or extended surfaces to increase the surface area exposed to a coolant, are also popular. Among active thermal control techniques, blown air, pumped water and circulated refrigerants are sometimes used. While these techniques may provide adequate thermal control properties for some applications, future design constraints will require improved temperature control systems. Furthermore, since many thermal control designs require a combination of heat removal techniques, new design tools are always welcome by thermal control designers, as new packaging configurations introduce new thermal control challenges.
Thermoelectric cooling (TEC) devices, such as, Peltier effect devices have been used in a variety of applications from consumer products (e.g., water coolers and wine cellar chillers) to laboratory, scientific and industrial products (e.g., test tube coolers, thermal baths). A typical thermoelectric module includes two ceramic substrates with doped P-type and N-Type semiconductive material (e.g., bismuth telluride) connected electrically in series and thermally in parallel between the ceramic substrates. Conductive pads (e.g., copper pads) are coupled to each semiconductive material and act as electrical contacts. A power source is coupled to the conductive pads. As current flows in series through the semiconductive materials, one ceramic substrate will become hotter than ambient temperature and the other ceramic substrate will become colder than ambient temperature.
U.S. Pat. No. 5,457,342 to Herbst, II discloses one prior device in which a thermoelectric device is coupled to the outside of an IC package. In this device, a heat conductive base plate is placed against the package of an IC. The cooling surface of a Peltier effect module is coupled to the base plate. A heat radiator assembly is coupled to the heating surface of the Peltier effect module, and a fan assembly is juxtaposed next to a heat-radiating portion of the heat radiator assembly. The fan assembly and Peltier effect module are powered in parallel by a 12 VDC power source. In operation, the Peltier effect module cools the top surface of the IC package, and the fan assembly and heat radiator assembly cool the heating surface of the Peltier effect module. In this device, however, the Peltier effect module is coupled to the outside of the IC package and, therefore, the heat that can be removed by the Peltier effect module is limited to that heat which makes it to the outside of the IC package.
U.S. Pat. No. 5,079,618 to Farnworth discloses another prior system in which a two-posted Peltier semiconductor is mounted to a support member for an IC package. A copper lead frame member, a heat sink member, and an IC or transistor are mounted thereon. Interconnect wires couple power input leads of the IC package to the IC and the Peltier effect device to provide power to the IC and the Peltier effect device. Although this system discloses a Peltier effect device inside an IC package, the package is a dual in-line package (DIP) and requires delicate internal wiring that makes the wiring susceptible to shorts or cracking. Furthermore, most ICs today that require added power dissipation are larger devices embodied in more advanced packaging, such as, ball grid array (BGA) packaging.
Accordingly, what is needed is a new thermal control system that overcomes the challenges of applying Peltier effect technology to advanced packaging systems, such as, BGA packaging.